Open standard RISC ISA

RISC-V

A modular open ISA used for education, research, embedded systems, Linux-capable cores, open hardware, compiler work, and architecture experimentation.

Linux ELFBare metal firmwareRTOSOpen hardware boards

ABI notes

RISC-V psABI defines integer/floating registers, calling convention, ELF relocations, code models, and toolchain behavior.

Privilege model

User, supervisor, hypervisor, and machine modes depending on implementation, with CSRs, traps, satp paging, and platform interrupt controllers.

Registers

Name	Aliases	Class	Role
x0	zero	Integer	Hardwired zero
x1	ra	Integer	Return address
x2	sp	Stack	Stack pointer
x5-x7, x28-x31	t0-t6	Integer	Caller-saved temporaries
x10-x17	a0-a7	Integer	Arguments and return values
x8-x9, x18-x27	s0-s11	Integer	Callee-saved registers
f0-f31	ft/fa/fs aliases	Floating	Floating-point ABI registers
CSRs	mstatus, satp, mtvec	Control/status	Privilege and machine control

Instruction groups

Base integer
ADDI, LUI, AUIPC, loads/stores, branches, JAL/JALR

Multiply/atomic
M extension arithmetic, A extension LR/SC and AMOs

Floating/vector
F/D floating point, V vector extension

Compressed
C extension 16-bit encodings for density

Privileged
CSR access, traps, fences, environment calls

Starter code

.globl _start
_start:
    li a7, 64
    li a0, 1
    la a1, msg
    li a2, 13
    ecall

    li a7, 93
    li a0, 0
    ecall
msg:
    .ascii "hello risc-v\n"